The present disclosure relates generally to chip manufacturing, and more particularly to methods, systems and computer program products of providing portion isolation design to a chip design to facilitate partial-good portion isolation test of a chip.
The rapid densification of very-large-scale integration (VLSI) devices, incorporating complex functions operating at extreme circuit performance, has driven the designs towards integrating many diverse functional macros or cores within these large chips. These macros range from autonomous processor cores with large cache arrays occupying relatively large portions of the chip's real estate, to a multitude of small arrays used as register stacks, trace arrays, content addressable memories, phase locked loops (PLLs), and many other special purpose logic functions. In conjunction with these higher integration densities and larger devices, current system architecture is shifting, in many applications, toward massively parallel processing utilizing multiple copies of these integrated cores. The number of processing cores can range from dual-cores to hundreds of cores per chip in the near future and to thousands of core arrays at system level. The independent logic units such as register stacks, trace arrays, content addressable memories, PLLs, as well as the cores in a processor are called “portions” of a chip here.
These highly integrated circuit functions, in conjunction with state-of-the-art semiconductor technology advances, usually result in relatively low device yields because even if one of the many portions of a chip is defective, then the entire chip is considered as defective. A further enhancement to the overall yield is to utilize partially “good” devices or devices that function acceptably with some defective portions.
The scenario outlined above surfaces several test and diagnostic problems that have driven the design and integration of many test functions within the same semiconductor devices.
Hierarchical Test and Partial Good Test testing needs portion wrapping to isolate one or more portion netlist from the logic outside its logical hierarchy. The wrapper resides at the boundary of the core and provides a way to test the portions of the semiconductor devices in isolation and also the interconnection between the various portions at its Top Level.
Therefore, heretofore unaddressed needs still exist in the art to address the aforementioned deficiencies and inadequacies.